EESP Workshop 2026

Objective

The EESP workshop fosters the exchange of innovative strategies, tools, and best practices to enhance energy efficiency in modern computing environments. With rising energy costs, increasing CO₂ emissions, and mounting pressure on power infrastructure, optimizing energy use has become a crucial priority for sustainable computing infrastructure. EESP workshop explores how to optimize computing environments by effectively balancing performance, power consumption, and sustainability trade-offs. It will provide participants a comprehensive guidebook featuring strategies tailored for exascale, Tier-1 and Tier-2 supercomputing centers. By learning about how to adopt greener, cost-effective, and energy-efficient practices, attendees will gain a competitive edge in driving sustainability across their systems. Aligned with the Sustainable Development Goals, the workshop encourages collaboration between HPC and AI communities to promote environmentally responsible innovation. It will provide guidance for system operators and facility managers on reducing Power Usage Effectiveness and sourcing green energy, while supporting users in making energy-conscious decisions through thoughtful experiment design. The workshop also emphasizes full-lifecycle sustainability -- from system design and operations to reuse and decommissioning -- and considers how HPC strategies can support energy-efficient AI infrastructure amid growing convergence. While current tenders often emphasize raw hardware metrics, this workshop highlights the importance of sustained (application) performance, rather than peak performance, as a critical metric for long-term success.

Scope

EESP invites academia, supercomputing centers, industry, national laboratories, and policymakers to collaborate on advancing energy-efficient practices. To achieve end-to-end visibility and adaptability in energy usage, EESP emphasizes cross-layer innovation, encompassing advances in hardware, software, runtime systems and system-application co-design. This includes data-driven analytics and monitoring, energy-efficient methodologies, operational case studies, benchmarking frameworks, AI–HPC convergence, and sustainability metrics that extend beyond energy efficiency, such as carbon emissions. The workshop fosters dialogue between Tier-0/1 and Tier-2 centers to help adapt Tier-0/1 innovations for more constrained budgets. While investment priorities differ across tiers, challenges in software and applications remain universal, serving as a unifying link. It targets financial and technical solutions applicable to HPC clusters, data centers, and cloud infrastructures worldwide.

Topics of Interest

The workshop aims to benefit the broader community by sharing use cases, lessons learned, and best practices through descriptive papers. To achieve the workshop's objectives and to address emerging challenges, we solicit papers which encompass the following topics of interest, but are not limited to:

• Energy-aware software and application optimization
• Programming models, compilers, and tools for energy-efficient computing
• Energy-efficient hardware architectures and design practices
• Energy-aware resource management, and power-steering runtimes
• Operating system and network techniques for power and thermal control
• Tools/frameworks for energy monitoring, instrumentation and analysis
• Processor and system energy models including behavioral insights
• Cluster-wide energy benchmarking and regression analysis
• Comparative benchmarking of node architectures and memory systems
• Analysis of long-term energy degradation in CPUs and GPUs
• Renewable energy sources for HPC systems
• Energy-efficient procurement frameworks and lifecycle cost analysis
• Operational analytics and control for real-time power adaptation
• Integration, energy/performance profiling and optimization of AI workloads
• Emerging trends and challenges in HPC/AI energy consumption

Call for Papers

The EESP Workshop 2026 invites submissions of research papers focused on energy efficiency and sustainable performance in high-performance computing and artificial intelligence.

• Submission Guidelines
  • Papers should be either short (work-in-progress, 6 pages) or regular (12 pages), including references and appendices.
  • Submitted papers must be original and not previously published or under review for any other conference or journal.
  • Use the Springer Lecture Notes in Computer Science (LNCS) template.
  • Submit papers in PDF format through the ISC Linklings submission system (Link: TBA).
• Review Process
  • Each submission will undergo a minimum of three single-blind peer reviews.
  • Review criteria include originality, technical soundness, impact, and quality of presentation.
  The Best Paper Award will be selected by the workshop program and organizing committee according to the established review criteria.
• Post-Submission
  • Accepted papers will be published as part of the ISC proceedings in the Springer LNCS series.
  • There is an option for submitting two additional pages after the review to address reviewer feedback.
  • One author must present the accepted paper in person and register for the ISC 'Workshop Pass.'
  • Information on travel, visas, accommodation, and attractions in Hamburg is available on the ISC 2026 website.
  • The Best Paper Award will be presented in person at the workshop.

Keynote Speech

Dr. John L. Gustafson Arizona State University and Vq Research

Every Bit Counts: Posit Computing for Energy-Efficient HPC and AI

Abstract Both the HPC and AI communities are increasingly adopting the posit arithmetic approach introduced by Dr. John L. Gustafson in 2017. By rethinking how numbers are represented and computed, posits offer a promising pathway toward energy-efficient high-performance computing, aligning with the goals of sustainable exascale systems. Traditional technical computing relies on numerical representations invented over a century ago (1914) and ad hoc number formats from nearly 50 years ago, designed for an era when transistors were expensive but electrical power was abundant. Persisting with these antiquated formats into the exascale era wastes power, energy, storage, bandwidth, and programmer effort. Unlike legacy floating-point formats, posits are mathematically closed, produce reproducible results across platforms, and dynamically allocate precision based on magnitude. This allows computers to save time, storage, energy, and power by encoding more information per bit and avoiding repeated computations or error corrections.
In this keynote, Dr. Gustafson will present recent developments in posit arithmetic. By providing enhanced precision and dynamic range with fewer bits, posits enable more accurate calculations while reducing energy and computational overhead. Posits also handle edge cases robustly, minimizing wasted cycles and memory accesses. The talk will explore theoretical foundations, practical implementation challenges, and the potential of posits to drive energy-efficient computation, offering a fresh design that delivers better answers with lower energy consumption.

BIO Dr. John L. Gustafson is a renowned computer scientist and pioneer in high-performance computing. He is best known for formulating Gustafson’s Law, the foundational alternative to Amdahl’s Law, which transformed the world’s understanding of massively parallel scalability and earned him the inaugural Gordon Bell Prize in 1988. Over the course of his career, he has led groundbreaking research at Sandia National Laboratories, where he introduced one of the world’s first commercial computer clusters and founded the Scalable Computing Laboratory. In industry, he has held senior and executive roles at Intel (Director and Lab Leader for energy-efficient and extreme-scale computing), AMD (Chief Graphics Product Architect and Senior Fellow), ClearSpeed Technology (CTO), and Massively Parallel Technologies (CEO). He created the unum and posit number systems, alternatives to IEEE floating-point that improve accuracy and energy efficiency. He has authored influential books (e.g., Every Bit Counts) and numerous highly cited papers on parallel performance, computer arithmetic, and HPC productivity. He holds applied mathematics degrees from Caltech and Iowa State University. Across academia and industry, Gustafson has been a visiting scholar, educator, and keynote speaker, and currently serves as Visiting Scholar at Arizona State University and Chief Scientist/Co-founder of Vq Research.

Workshop General Chair

Ayesha Afzal - Erlangen National High Performance Computing Center (NHR@FAU), Geramny

Program Co-Chairs

• Natalie Bates - Energy Efficient HPC Working Group (EE HPC WG), USA
• Hatem Ltaief - King Abdullah University of Science and Technology (KAUST), Saudi Arabia
• Bronis R. de Supinski - Lawrence Livermore National Laboratory (LLNL), USA

Program Committee

Collaborators

• Erlangen National High Performance Computing Center (NHR@FAU)
• Energy Efficient HPC Working Group (EE HPC WG)

Past Edition

← EESP 2025

Contact

For questions, please contact the General Chair: Ayesha Afzal at ayesha.afzal@fau.de.

Announcements

Call for Paper Open and keynote announced!

Keynote speech by John Gustafson has been announced and paper submission for EESP 2026 proceedings is open. Check the technical details here.

Important Dates

• Submission deadline: March 1, 2026, AoE
• Notification: April 14, 2026, AoE
• Camera ready deadline: May 26, 2026, AoE
• Workshop date: June 26, 2026

EESP 2026 Statistics Highlights

• Highest 3/3 score in ISC workshop proposal review
• Keynote by John Gustafson, ASU & Vq Research
• Others: TBA

EESP 2025 Statistics Highlights

• 22 papers received from 11 countries
• 4.9/5 score in ISC post-evaluation survey
• 37 committee members across 16 countries
• 40 attendees (overlap with ISC tutorials)
• 4 sessions by 4 chairs from 4 countries
• Keynote by John Shalf, LBNL
• Best Paper: “What A Waste,” Queen's University